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Computer Engineering, Microcontrollers Motorolla

 

Lab Objectives

The objective for this lab is to review the Motorola assembly language instruction set using digital logic gates. This lab will also serve as a review of digital logic and introduce the concept of coding logic designs in assembly.

 

Description

In this lab, you will overview the assembly logic instructions that can be used for logic gates. A logic gate is an idealized or physical device implementing a Boolean function, that is, it performs a logical operation on one or more logic inputs and produces a logic output(s). You will then use these logic gates to create a logic circuit in assembly.

 

Work Task

Design, implement, and test the following logic gates. For parts 1-4, your code must reside on the EEPROM (ROM). For parts 5 and 6, your code must be in program section of RAM (PROG). And your variables must reside in the data section of RAM (DATA). You must use the assembly logic instructions available to you (e.g., ANDA for the AND gates).

 

1.     NOT Gate

The overall objective is to create a NOT gate. The system has one digital input and one digital output, such that the output is the logical complement of the input. Investigate the complement (i.e., COMA and COMB) and the BCLR instructions.

 

 

 

IN

OUT

0

1

1

0

 

2.     3-Input AND Gate

The overall objective is to create a 3-input AND gate. The system has three digital inputs and one digital output, such that the output is the logical AND of the three inputs. Investigate the AND instruction (i.e., ANDA or ANDB).

 

 

 

IN 1

IN 2

IN 3

OUT

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

 

3.     3-Input OR Gate

The overall objective is to create a 3-input OR gate. The system has three digital inputs and one digital output, such that the output is the logical OR of the three inputs. Investigate the OR instruction (i.e., ORAA or ORAB).

 

 

 

IN 1

IN 2

IN 3

OUT

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

1

 

4.     2-Input XOR Gate

The overall objective is to create a 2-input XOR gate. The system has two digital inputs and one digital output, such that the output is the logical XOR of the two inputs. Investigate the XOR instruction (i.e., EORA or EORB).

 

 

 

IN 1

IN 2

OUT

0

0

0

0

1

1

1

0

1

1

1

0

 


 

5.     Sum-of-Products (SoP)

Using the sum-of-products expression, find and code the simplified logic function for Table 1 using the assembly logic instructions. Show your work in the discussion section of your report (i.e., k-maps and digital logic schematic).

A

B

C

F

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1

Table 1: Truth table 1.

6.     Product-of-Sums (PoS)

Using the products-of-sums expression, find and code the simplified logic function for Table 2 using the assembly logic instructions. Show your work in the discussion section of your report (i.e., k-maps and digital logic schematic).

A

B

C

D

F

0

0

0

0

1

0

0

0

1

1

0

0

1

0

0

0

0

1

1

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

0

0

0

1

1

0

0

1

0

1

0

1

0

0

1

0

1

1

0

1

1

0

0

1

1

1

0

1

1

1

1

1

0

1

1

1

1

1

1

Table 2: Truth table 2.

What to Turn In (Please read this carefully)

You are to put your code as text and screenshots into the “Lab_2_Template.docx” in the designated areas. This will be the file that you upload to TITANium as your submission. Provide your code as text, not an image. Points will be deducted if it is an image. You are then to take screenshots of your program in both CodeWarrior and terminal (i.e. on the Dragon board). The screenshot should show the relevant CPU registers and memory locations (NOTE: a convenient way of getting screenshots is to use the “snipping tool”).

 

For the logic design portion for parts 5 and 6, turn in your design (i.e., k-maps and digital logic schematic) for as a paper submission. No logic design is required for parts 1 to 4.

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